1) Field of the Invention
This invention relates generally to formation of wells in a semiconductor substrate and more particularly to the formation of both n-wells and p-wells using a single photo masking step.
2) Description of the Prior Art
In the fabrication of CMOS devices it is frequently desirable to make a complimentary or symmetric environment with respect to the NMOS and PMOS devices. In other words, it is frequently necessary to create suitable n-type regions for the PMOS devices and suitable p-type regions for the NMOS devices. Each of these n-type and p-type regions is generally referred to as a "well". Currently, when n-wells and p-wells are formed in the same substrate, they are formed using two separate masking steps.
It is known that formation of such n-wells and p-wells may be acheived by the implantation of an appropriate dopant species, such as boron or phosphorus, into a suitable substrate followed by high temperature drive-in of the implanted ions.
One typical process is a two-mask, self-aligned LOCOS twin-well process with two separate well implants. First, a photo resist layer is formed covering the p-well regions. Then n-type impurities are implanted into the n-well regions of the substrate and the first photo resist layer is removed. Next, a thick masking oxide (LOCOS) is selectively grown over the n-well regions. This masking oxide consumes a significant depth of the silicon surface and causes topography that can interfere with subsequent overlaying layers. The masking oxide (LOCOS) typically has a thickness in a range between about 2,000 and 6,000 .ANG. and consumes a depth of the silicon substrate in a range between about 1,000 and 3,000 .ANG.. Then, using the masking oxide (LOCOS) as an implant mask, p-type impurities are implanted into the p-well regions of the substrate. The masking oxide is removed by a selective etching process, forming depressions in the substrate surface. A nitride masking layer is deposited and patterned to cover the active areas using a second resist layer. As device size is reduced and device density is increased, the alignment of separate masks becomes increasingly critical, reducing yields and requiring costly additional inspection procedures. A field oxide is formed over non-active areas and overlaps the n well and p well borders. The process creates rugged topography by forming the LOCOS masking layer and the field oxide regions. The substrate surface is lower in the n well region where the oxide masking layer (LOCOS) consumed the silicon substrate. Finally, a thermal treatment is used to drive-in of the implanted ions to obtain adequate well depth. This thermal treatment causes well impurity concentrations to decrease by mutual impurity diffusion at the boundary region of adjacent n-wells and p-wells. The decrease in well impurity concentration induces increased susceptibility to latch-up because of the increased current gain of the parasitic bipolar transistors in the well structure. Several two-mask variations are known, but they all have the same mask alignment problem and require the expense of two separate photolithography steps.
Several single mask processes are also known. Sung (5,573,963) discloses a one photo mask, self-aligned twin well process using BPSG layer as an implant mask. The process begins by forming spaced field oxide regions in a substrate defining first regions (e.g. n-wells) and second regions (e.g. p-wells). An ion implant masking layer composed of borophosphosilicate glass (BPSG), and a nitride barrier layer are formed over the field oxide regions and the substrate. Using a patterned photoresist layer, the nitride barrier layer and upper portions of the BPSG masking layer over the n-well regions are anisotropically etched. The photoresist layer is then removed. Next, the remaining BPSG masking layer over the n-well region is selectively etched. N-type impurities are implanted into the n-well region using the nitride layer and BPSG masking layer as an implant mask. P-type impurities are then implanted into the substrate, forming a p-type layer beneath the n-well regions and in the p-well regions. The nitride layer and BPSG layer are removed, and the substrate is annealed to drive in the implanted impurities, thereby forming n-wells and p-wells. As with the LOCOS process, the thermal drive-in of implanted ions increases the susceptibility to latch-up.
Horiuchi, et. al.; "A 7-MASK CMOS PROCESS WITH SELECTIVE OXIDE DEPOSITION", (IEEE TRANSACTIONS ON ELECTRON DEVICES, Vol. 40, No. 8, August, 1993) discloses a one-mask, twin well process using a selective liquid phase oxide deposition (LPD) process. After the first implants masked by photoresist, the LPD process is used to create an oxide mask over the first well regions for the second implants. The LPD process can deposit a mask of sufficient thickness for high energy implants for retrograde well formation. Retrograde well formation eliminates the need for thermal drive-in, increasing well impurity concentrations and decreasing latch-up susceptibility.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering: U.S. Pat. No. 5,393,677(Lien) shows a one mask method for forming twin P/N wells. U.S. Pat. No. 5,252,501(Moslehi) shows a method of forming a single mask twin wells. U.S. Pat. No. 5,506,438(Hsue) discloses a semiconductor device having twin wells. U.S. Pat. No. 5,091,332(Bohr) teaches a method for forming twin wells and FOX. U.S. Pat. No. 5,547,894(Mandelman) shows a method for forming p and N wells. U.S. 5,583,062(Kapoor) teaches a method Self-aligned twin wells having a SiO.sub.2 /poly/SiO.sub.2 barrier mask. U.S. Pat. No. 5,670,395(Pan) shows a method for forming self-aligned twin P/N wells that uses a conformal oxide or spin-on-glass oxide that is less than optimal for gap filling small openings.